1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a column command buffer of a semiconductor memory apparatus and a latency circuit including the same.
2. Related Art
A semiconductor memory apparatus performs a read operation and a write operation in response to a read command and a write command which are inputted from outside through a pad. Since the read operation and the write operation are related to column operations of the semiconductor memory apparatus, the read command and the write command are also called column commands. The column commands are converted into internal column commands through column command buffers. Currently, in a semiconductor memory apparatus, specifically, a DRAM (dynamic random access memory), a CAS latency is defined and used. The CAS latency means a time from when a read command is inputted till the data of the semiconductor memory apparatus is outputted. When the read command is inputted, the semiconductor memory apparatus generates an internal read signal by delaying an internal column command generated from the read command by a clock cycle corresponding to the CAS latency. The semiconductor memory apparatus performs a read operation in response to the internal read signal.
In a semiconductor memory apparatus developed since the advent of DDR2, an additive latency has been proposed to be used. The additive latency means a time, when a semiconductor memory apparatus is activated, from when a read or write command is inputted to a tRCD (RAS to CAS Delay). The tRCD defines a time from when a row address signal is inputted till a column address signal is inputted. In a semiconductor memory apparatus developed before DDR2, a read or write command can be inputted only after the tRCD. However, in a semiconductor memory apparatus since DDR2, because a read or write command can be inputted more quickly by the additive latency, the responding speed of the semiconductor memory apparatus can be increased. The additive latency can be set in an EMRS (extended mode register set). For example, the additive latency can be set as AL=0, AL=CL-1 or AL=CL-2.
Accordingly, when a column command is inputted, the semiconductor memory apparatus performs the read operation by delaying the column command by a clock cycle corresponding to the additive latency and the CAS latency.
FIG. 1 is a block diagram schematically illustrating a configuration of a conventional latency circuit. Referring to FIG. 1, a conventional latency circuit includes a column command buffer unit 10, an additive latency shifting unit 20, and a CAS write latency shifting unit 30. The column command buffer unit 10 receives a column command CASP6 and generates first and second internal column commands CASP8_NON_AL0 and CASP8_AL0. When an additive latency is 0, the column command buffer unit 10 generates the second internal column command CASP8_AL0 in response to a control signal AL0 inputted from a mode register set. The column command buffer unit 10 does not generate the second internal column command CASP8_AL0 when the additive latency is CL-1 or CL-2.
The additive latency shifting unit 20 receives the first and second internal column commands CASP8_NON_AL0 and CASP8_AL0 and control signals ALCL_1 and ALCL_2 and generates an internal read signal RD_int. The additive latency shifting unit 20 may include a plurality of flip-flops (not shown) and a plurality of pass gates (not shown). The additive latency shifting unit 20 outputs the second internal column command CASP8_AL0 as the internal read signal RD_int when the second internal column command CASP8_AL0 is inputted. When the first internal column command CASP8_NON_AL0 is inputted, the additive latency shifting unit 20 generates the internal read signal RD_int by delaying the first internal column command CASP8_NON_AL0 by a clock cycle corresponding to a CAS latency CL<5:11> and the additive latency through the plurality of flip-flops and the plurality of pass gates. The semiconductor memory apparatus performs a read operation in response to the internal read signal RD_int.
The CAS write latency shifting unit 30 generates an internal write signal WT_int by delaying the internal read signal RD_int according to a CAS write latency CWL<5:8>. Similar to the additive latency shifting unit 20, the CAS write latency shifting unit 30 may include a plurality of flip-flops (not shown) and a plurality of pass gates (not shown), and can delay the internal read signal RD_int by a clock cycle corresponding to the CAS write latency CWL<5:8>.
FIG. 2 is a circuit diagram illustrating a configuration of the column command buffer unit shown in FIG. 1. The column command buffer unit 10 receives the column command CASP6 and generates the first and second internal column commands CASP8_NON_AL0 and CASP8_AL0. Referring to FIG. 2, the column command buffer 10 includes a delay section DLY, first to third inverters IV1-IV3, first and second PMOS transistors P1 and P2, and first and second NMOS transistors N1 and N2. The delay section DLY delays the column command CASP6 by a predetermined time. The first and second inverters IV1 and IV2 sequentially invert the output of the delay section DLY and generate the first internal column command CASP8_NON_AL0. The third inverter IV3 inverts the control signal AL0. When the control signal AL0 is enabled, the first PMOS transistor P1 and the first NMOS transistor N1 respectively receive the output of the third inverter IV3 and the control signal AL0 and thus are turned on. Since the second PMOS transistor P2 and the second NMOS transistor N2 operate as an inverter when the first PMOS transistor P1 and the first NMOS transistor N1 are turned on, the second PMOS transistor P2 and the second NMOS transistor N2 invert the output of the first inverter IV1 and generate the second internal column command CASP8_AL0.
The first internal column command CASP8_NON_AL0, which is generated in the column command buffer unit 10, is delayed by a clock cycle corresponding to the additive latency through the additive latency shifting unit 20 including the plurality of flip-flops as described above. The second internal column command CASP8_AL0 is provided as the internal read signal RD_int to the CAS write latency shifting unit 30 and is delayed by the CAS write latency shifting unit 30.
FIG. 3 is a circuit diagram illustrating one embodiment of a flop-flop in the additive latency shifting unit or the CAS write latency shifting unit shown in FIG. 1. Referring to FIG. 3, a flip-flop 21 includes a fourth inverter IV4, a fifth inverter IV5, a first pass gate PG1, a second pass gate PG2, a first latch section 21-1, and a second latch section 21-2. The first pass gate PG1 transmits the first internal column command CASP8_NON_AL0 (in the case of the flip-flop of the additive latency shifting unit 20) or the internal read signal RD_int (in the case of the flip-flop of the CAS write latency shifting unit) (since the second internal column command CASP8_AL0 is provided as the internal read signal RD_int without being delayed, the second internal column command CASP8_AL0 and the internal read signal RD_int are given together in FIG. 3) to a first node NA in response to a clock CLK and the clock inverted by the fourth inverter IV4. The first latch section 21-1 latches the level of the first node NA, and the second pass gate PG2 transmits the signal of the output node of the first latch section 21-1, that is, a second node NB, to a third node NC in response to the clock CLK and the clock inverted by the fifth inverter IV5. The second latch section 21-2 latches the level of the third node NC and generates an output signal OUT. Accordingly, the first pass gate PG1 outputs the first internal column command CASP8_NON_AL0 or the internal read signal RD_int when the clock CLK is at a high level, and the second pass gate PG2 outputs the signal of the second node NB when the clock CLK is at a low level.
FIG. 4 is a timing diagram illustrating operations of the flip-flop shown in FIG. 3 depending upon the frequency of a clock. Referring to FIG. 4, operations of the semiconductor memory apparatus with a clock of a high frequency and a clock of a low frequency are shown together. Due to the characteristics of clock signal, a clock of a high frequency has a steep slope, and a clock of a low frequency has a gentle slope. The delay section DLY of the column command buffer unit 10 delays the column command CASP6 such that the flip-flop of the additive latency shifting unit 20 or the flip-flop of the CAS write latency shifting unit 30 can precisely latch the first internal column command CASP8_NON_AL0 or the internal read signal RD_int or the second internal column command CASP8_AL0. However, in the case of a semiconductor memory apparatus operating with a clock of a low frequency, since the slope of the clock is very gradual, the flip-flop of the additive latency shifting unit 20 or the flip-flop of the CAS write latency shifting unit 30 may not precisely latch the first internal column command CASP8_NON_AL0 or the internal read signal RD_int.
Referring to FIG. 4, in the semiconductor memory apparatus operating with a clock of a high frequency, the flip-flop 21 normally latches and outputs the first internal column command CASP8_NON_AL0 or the internal read signal RD_int. However, in the semiconductor memory apparatus operating with a clock of a low frequency, falling of the clock CLK occurs after the first internal column command CASP8_NON_AL0 or the internal read signal RD_int falls to a low level, that is, the first internal column command CASP8_NON_AL0 or the internal read signal RD_int is at a low level at the first falling of the clock CLK. As a consequence, a period during which the first node NA has a high level is not sufficiently sustained, and, accordingly, the output signal OUT is not generated. In particular, such problem becomes serious when the second internal column command CASP8_AL0 is directly provided as the internal read signal RD_int according to the control signal AL0.
Thus, a method for generating an internal column command so as to generate the internal read signal or the internal write signal from a column command without error regardless of the changes of a clock's frequency is required.